x86/amd OpCache Isolation

Vulnerability analysis

The vulnerability stems from improper isolation of shared resources in AMD Zen2's operation cache, which can cause instruction corruption when multiple processes or security contexts share CPU resources. The root cause is missing initialization of a hardware bug fix bit (MSR_ZEN2_BP_CFG_BUG_FIX_BIT) in the branch predictor configuration MSR during CPU initialization. The fix adds code to set bit 33 in MSR 0xc001102e during Zen2 CPU initialization, but only when not running under a hypervisor (to avoid conflicts with hypervisor management). This ensures proper isolation of op cache resources and prevents cross-context instruction corruption. The attack surface is local, requiring code execution on the target system to exploit the shared resource vulnerability.